M.Manobala, N.Manikanda Deverajan, Dr.A.Nagappan, Dr.D.Vinod Kumar
The FFT architecture was reconfigurable for supporting both variable length and multistreaming. They are able to process architecture in 1 stream of 2048-pt FFT or two streams of 1024-pt FFT or 4 stream of 512-pt FFT. The architecture having SDF pipelined stages and in each stage radix-2 butterfly is calculate. The sampling frequency is changed in depend upon the FFT length. The word length and buffer length in each stage is calculate by FFT length. Power consumption was decreases by use of latch gating. Experimental result show that the design increase the throughput expected by the Wi-Max standard. The architecture used fewer amounts of the total available FPGA resources and clock frequency of the system was 13.67 MHz achieved.