నైరూప్య

Design of an Efficient Low power Shift Register using Double Edge Triggered Flip-flop

Renganayaki G , Jeyakumar.V

In this paper it is proposed to implement low-power shift register using double edge triggered flip-flops and make comparison analysis of existing double edge triggered flip-flops. The flip-flops(FF) in the proposed shift register are designed using clock branch-sharing implicit pulsed scheme(CBS_ip). The various existing double edge triggered flip-flops are transmission-gate latch-MUX, C2MOS Latch-MUX, Dual-edge transmission-gate pulsed latch (DE-TGPL). The main feature of the clock branch-sharing scheme is to reduce the number of clocked transistors in the design as compared with existing double edge triggering flip-flops. As compared to the other state of the art double-edge triggered flip-flop designs, this CBS_ip design has an improvement in power consumption .