నైరూప్య

DESIGN OF IMPROVED MAJORITY LOGIC FAULT DETECTOR/CORRECTOR BASED ON EFFICIENT LDPC CODES

G.Boopathi Raja, Dr.M.Madheswaran

Memory is responsible for any digital circuit for storing as well as retrieving any data that are needed at particular time. Encoding and Decoding are the two basic operations that are responsible for reading and writing. Nowadays, single event upsets (SEUs) altering digital circuits are becoming a bigger concern for memory applications. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method uses difference-set cyclic codes instead of several other block codes such as BCH code, Hamming code, RS code, etc. This method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low. The proposed method detects the occurrences of single error, double error ,triple error in the received code words obtained from the memory system. The proposed fault-detection method uses a special class of Low Density Parity Check (LDPC) codes especially Difference-set Cyclic Codes (DSCC) significantly reduces memory access time when there is no error in the data read.