నైరూప్య

Design of Transposed Polyphase Decimation Filter Using Dadda Multiplier

M.Ramya, S.Jeevitha

Power has become a major issue in modern VLSI design. In digital signal processing systems, multiplier plays an important role but also it consumes more power and area. While using BFD multiplier for designing transposed polyphase decimation filter, it has more dynamic power dissipation which is due to the increased switching activity during multiplication and consumes a large circuit area. Also, the number of addition depends on the number of multiplicand bits which cannot be reduced. To overcome these drawbacks, Dadda multiplier is used for better performance as much as compared to existing system.